The number of input and output pins on today's ever increasingly smaller integrated circuits is decreasing, while the available computing power is ever increasing, especially in modern microprocessors, microcontrollers, and the like. In addition, the quantity of data that is processed by these systems also is increasing. This has given rise to the development of so-called “serdes” devices.
“Serdes” is an acronym for a “serializer/deserializer” device. A serdes device receives an n-bit parallel data stream and converts it to a one-bit serial data stream for transmission over a serial transmission line, or channel, to a receiver. At the receiver, the device deserializes the serial data stream back to its original parallel form for use, for example in a processor, controller, or device requiring a parallel data input. The value of n may be any value greater than two; however, a value of 8 or 10 is typically be used for many coding protocols.
Also, although the term “device” is used to describe a single serdes device, it should be understood that serdes devices may comprise a plurality of separate chips, notably a transmitter and a receiver, with an interconnecting serial channel. The various chips, moreover, may reside or be embedded in different circuit elements, such as within a bus controller and a microcontroller, or the like. On the other hand, the various serdes device parts may be consolidated on a single chip, for example, when it is impractical to run a large data bus from one side of a chip to the other.
In order for the data to be properly converted from parallel data to serial data at the transmitting end, an accurate clock is required. In some serdes embodiments, the clock generator is driven by a phase-locked loop (PLL). One requirement of the PLL is that it delivers a high quality clock with minimal random jitter.
The PLLs typically employ a voltage-controlled oscillator (VCO) that must operate over a wide range of frequencies in order to meet demanding timing requirements of serdes devices. The speed of the transistors used in the VCO, however, may vary, depending on chip process, voltage, and temperature (PVT) conditions. All possible PVT variations from the ideal PVT conditions are often referred to as “corners,” and the operation of the particular circuit under consideration under various PVT conditions is sometimes referred to as operation “within the corners.” Thus, PLLs used in serdes devices need to support a wide range of frequencies over multiple corners. In cutting-edge silicon technologies, like 28 nm, this requires a very high VCO gain (dfVCO/dVCTRL). However, reaching high PLL frequencies is difficult for slow corner conditions because the VCO will run slower than for fast corner conditions.
Large VCO gain increases the jitter contribution of the loop filter's resistance on the PLL output clock. Moreover, a PLL having a large VCO gain would require a large loop capacitor to provide the desired loop bandwidth with peaking of less than, for example, 1 dB.
What is needed is a method and circuit for reducing the VCO gain, kVCO, thermal noise produced by the loop resistor, and the size of the loop capacitance required for a desired loop bandwidth with peaking of less than 1 dB. Also needed is a method and circuit that supports a high VCO frequency range. Additionally needed are circuit embodiments that are dynamic to adjust to changes in PVR conditions, including corners introduced by systematic and random variations of the transistors in the chip.